Measuring True Jitter Performance of High Speed Clocks
As the data rates in high-speed digital designs increase, the limits for overall system jitter become tighter. This especially applies to the various components of the clock tree, where the jitter limits for reference clocks, clock buffers and jitter attenuators are even tighter. PCIe Gen4, for example, introduces data rates of up to 16 gigatransfers per second (GT/s) with a corresponding jitter limit of 500 fs (RMS) for the reference clock. To minimize EMI effects, technologies like PCIe, USB and HDMI™ typically use spread spectrum clocking (SSC), applying a low-frequency. Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice for these tests.
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